use clap::{Parser, Subcommand};

#[derive(Parser)]
#[command(name = "moparse")]
#[command(about = "Verilog模块解析器 - Rust版本", long_about = None)]
#[command(version = "1.0.0")]
#[command(author = "CrystalFlowAnalyzer Team")]
pub struct Cli {
    #[command(subcommand)]
    pub command: Commands,
}

#[derive(Subcommand)]
pub enum Commands {
    /// 解析 Verilog 文件
    Parse {
        /// Verilog 输入文件
        #[arg(short = 'v', long)]
        verilog: Option<String>,
        
        /// Verilog 文件列表
        #[arg(short = 'f', long)]
        filelist: Option<String>,
        
        /// 输出 .modb 文件
        #[arg(short = 'o', long)]
        output: Option<String>,
        
        /// 合并到现有 .modb 文件
        #[arg(short = 'e', long)]
        existing: Option<String>,
        
        /// 指定模块名
        #[arg(short = 'm', long)]
        module: Option<String>,
        
        /// 解析所有模块
        #[arg(long)]
        all: bool,
    },
    
    /// 显示 .modb 文件信息
    Show {
        /// .modb 文件路径
        #[arg(short = 'i', long)]
        input: Option<String>,
        
        /// 模块名
        #[arg(short = 'm', long)]
        module: Option<String>,
        
        /// 详细级别 (-v: 显示参数/端口/实例, -vv: 额外显示wire信息)
        #[arg(short = 'v', long, action = clap::ArgAction::Count)]
        verbose: u8,
    },
    
    /// 删除模块
    Delete {
        /// .modb 文件路径
        #[arg(short = 'i', long)]
        input: String,
        
        /// 要删除的模块名
        #[arg(short = 'd', long = "dm")]
        module: String,
    },
    
    /// 显示模块层次结构
    Hierarchy {
        /// .modb 文件路径
        #[arg(short = 'i', long)]
        input: String,
        
        /// 模块名
        #[arg(short = 'm', long)]
        module: String,
        
        /// 最大显示层次深度 (0表示显示所有层次, 默认为1)
        #[arg(short = 'l', long, default_value = "1")]
        level: usize,
        
        /// 输出CSV文件路径（可选）
        #[arg(short = 'o', long)]
        output: Option<String>,
    },
    
    /// 反向生成 Verilog 代码
    Generate {
        /// .modb 文件路径
        #[arg(short = 'i', long)]
        input: String,
        
        /// 模块名
        #[arg(short = 'm', long)]
        module: String,
        
        /// 输出文件（可选，不指定则打印到标准输出）
        #[arg(short = 'o', long)]
        output: Option<String>,
        
        /// 生成模式 (e: 空壳, es: 空壳+stub, a: 完整, i: 实例)
        #[arg(long, value_parser = ["e", "es", "a", "i"])]
        mode: String,
    },
    
    /// 模块比较
    Compare {
        /// 第一个 .modb 文件
        #[arg(short = 'i', long)]
        input: String,
        
        /// 第一个模块名
        #[arg(short = 'm', long)]
        module: String,
        
        /// 第二个 .modb 文件
        #[arg(short = 'r', long)]
        reference: String,
        
        /// 第二个模块名
        #[arg(long = "rm")]
        ref_module: Option<String>,
    },
    
    /// Display signal connections between modules (similar to Verdi's trace feature)
    Connect {
        /// .modb file path
        #[arg(short = 'i', long)]
        input: String,
        
        /// Top module name
        #[arg(short = 'm', long)]
        module: String,
        
        /// Source module (can be hierarchical path, e.g., sub_a.sub_b)
        #[arg(long = "from")]
        from: Option<String>,
        
        /// Use top module as signal source
        #[arg(long = "from-top")]
        from_top: bool,
        
        /// Feedthrough module list (can have multiple)
        #[arg(long = "fd")]
        feedthrough: Vec<String>,
        
        /// Target module (can be hierarchical path)
        #[arg(long = "to")]
        to: Option<String>,
        
        /// Use top module as signal target
        #[arg(long = "to-top")]
        to_top: bool,
        
        /// Show tie-off ports (ports tied to constants)
        #[arg(long = "tie")]
        tie: Option<String>,
        
        /// Query all connections for a signal name
        #[arg(short = 's', long)]
        signal: Option<String>,
        
        /// Verbose mode: display wire names between modules
        #[arg(short = 'v', long)]
        verbose: bool,
        
        /// Exclude ports containing specified strings (can have multiple -e flags)
        #[arg(short = 'e', long = "exclude")]
        exclude: Vec<String>,
        
        /// Group ports by direction and generate demo assign code
        #[arg(short = 'g', long = "group")]
        group: bool,
        
        /// Source Verilog file path (for feedthrough modification with -p)
        #[arg(short = 'p', long)]
        source: Option<String>,
        
        /// Output Verilog file path (for feedthrough modification with -o)
        #[arg(short = 'o', long)]
        output: Option<String>,
        
        /// Modify source file in-place (combines -p and -o, overwrite source file)
        #[arg(long = "po")]
        source_inplace: Option<String>,
        
        /// Enable debug mode (show detailed replacement logs)
        #[arg(long = "debug")]
        debug: bool,
        
        /// Sort ports by direction (input->output or output->input)
        #[arg(long = "sort")]
        sort: bool,
        
        /// CSV output file for connection results
        #[arg(long = "csv")]
        csv: Option<String>,
        
        /// CSV ft_type parameter
        #[arg(long = "ft-type")]
        ft_type: Option<String>,
        
        /// CSV pass_instances parameter
        #[arg(long = "pass-instances")]
        pass_instances: Option<String>,
        
        /// CSV clock parameter
        #[arg(long = "clock")]
        clock: Option<String>,
        
        /// CSV reset parameter
        #[arg(long = "reset")]
        reset: Option<String>,
        
        /// CSV reset_to parameter
        #[arg(long = "reset-to")]
        reset_to: Option<String>,
        
        /// CSV port_format parameter
        #[arg(long = "port-format")]
        port_format: Option<String>,
        
        /// CSV port_format parameter with auto mode (use wire name)
        #[arg(long = "port-format-auto")]
        port_format_auto: bool,
        
        /// CSV repeater_module parameter
        #[arg(long = "repeater-module")]
        repeater_module: Option<String>,
    },
    
    /// Interactive shell or batch mode
    Shell {
        /// .modb file path to load
        #[arg(short = 'i', long)]
        input: String,
        
        /// Batch script file (optional, if not provided enters interactive mode)
        #[arg(short = 'f', long)]
        script: Option<String>,
        
        /// Global sort flag for shell mode (affects all commands)
        #[arg(long)]
        sort: bool,
        
        /// CSV output file for connect command results
        #[arg(long)]
        csv: Option<String>,
        
        /// CSV ft_type parameter (global for shell mode)
        #[arg(long = "ft-type")]
        ft_type: Option<String>,
        
        /// CSV pass_instances parameter (global for shell mode)
        #[arg(long = "pass-instances")]
        pass_instances: Option<String>,
        
        /// CSV clock parameter (global for shell mode)
        #[arg(long = "clock")]
        clock: Option<String>,
        
        /// CSV reset parameter (global for shell mode)
        #[arg(long = "reset")]
        reset: Option<String>,
        
        /// CSV reset_to parameter (global for shell mode)
        #[arg(long = "reset-to")]
        reset_to: Option<String>,
        
        /// CSV port_format parameter (global for shell mode)
        #[arg(long = "port-format")]
        port_format: Option<String>,
        
        /// CSV port_format parameter with auto mode (use wire name) (global for shell mode)
        #[arg(long = "port-format-auto")]
        port_format_auto: bool,
        
        /// CSV repeater_module parameter (global for shell mode)
        #[arg(long = "repeater-module")]
        repeater_module: Option<String>,
    },
}

impl Cli {
    /// 解析命令行参数
    pub fn parse_args() -> Self {
        Self::parse()
    }
}
